The present invention relates to an image display device for displaying an image based on an inputted display signal, and to an image display controller and a display control method for controlling the image display device.
As the image display device of such a type, for example, an active matrix liquid crystal display device using a switching element of a thin-film transistor (abbreviated to TFT, hereinafter) has been known. As shown in FIG. 8, a main portion of such a liquid crystal display device 50 includes, for example, a liquid crystal display panel 51 and a driving circuit unit.
The liquid crystal display panel 51 includes a liquid crystal material sealed between a TFT array substrate and a counter substrate disposed with a predetermined gap therefrom.
The TFT array substrate includes pluralities of signal lines S(1), S(2), xxx S(i), xxx S(N) and scanning signal lines G(1), G(2), xxx G(j), xxx G(M) disposed on a transparent insulating substrate 100 such as a glass substrate in a matrix form. At each intersecting portion of the signal lines and the scanning signal lines, a switching element 102, which is composed of a TFT and connected to a pixel electrode 103, is formed. An orientation film is provided so as to cover almost the entire surface of such components. Accordingly, the TFT array substrate is formed.
In addition, the counter substrate is formed by successively laminating a counter electrode 101 and an orientation film on the entire surface of a transparent insulating substrate such as a glass substrate as in the case of the TFT array substrate.
The driving circuit unit includes a scanning signal line driving circuit (gate driver) 300 connected to each of the scanning signal lines, a signal line driving circuit (source driver) 200 connected to each of the signal lines, and a counter electrode driving circuit COM connected to the counter electrode 101.
The scanning signal line driving circuit 300 includes, for example as shown in FIG. 9, a shift register unit 300a composed of cascade-connected flip-flops F1, F2, xxx amounting to M in number, and selecting switches 300b for switching in accordance with outputs from the respective flip-flops. A gate on voltage Vgh enough to turn on the switching element 102 (see FIG. 8) is applied to one input terminal VD1 of each of the selecting switches 300b. A gate off voltage Vgl enough to turn off the switching element 102 is applied to the other input terminal VD2. Accordingly, when a data signal (GSP) sequentially transferred through the flip-flops F1, F2, xxx by a clock signal (GCK) is successively outputted to the selecting switches 300b, each of the selecting switches 300b selects in response the voltage Vgh for turning on the switching element 102 for one scanning period (TH), outputs the voltage Vgh to each of scanning signal lines 105, and then outputs the voltage Vgl for turning off the switching element 102 to each of the scanning signal lines 105. This operation enables a video signal outputted from the signal line driving circuit 200 to each of signal lines 104 (see FIG. 8) to be written into each corresponding pixel.
FIG. 10 shows an equivalent circuit of one display pixel P(i, j) constructed in a manner that a pixel capacitance CIc and an auxiliary capacitance Cs are connected in parallel with each other to a counter potential of a counter electrode driving circuit COM. In the drawing, a reference code Cgd denotes a parasitic capacitance between a gate and a drain of the switching element 102.
Next, description will be made for a driving method of the liquid crystal display device 50. It is widely known that a liquid crystal needs AC driving to prevent a residual burned image and display deterioration, and a conventional driving method described below employs frame inversion driving, which is a kind of such AC driving.
FIG. 11 shows a driving waveform of the liquid crystal display device 50. In FIG. 11, a reference code Vg denotes a waveform of one scanning signal line; Vs denotes a waveform of one signal line; and Vd denotes a drain waveform.
As shown in FIG. 11, in a first field (TF 1), when a scanning voltage Vgh as shown in FIG. 11 is applied from the scanning signal line driving circuit 300 to the scanning line G(j) (see FIGS. 8 and 9), the switching element 102 connected to the scanning line G(j) is turned on. A video signal voltage Vsp from the signal line driving circuit 200 is written through source and drain electrodes of the switching element 102 into the pixel electrode 103. The pixel electrode 103 holds a pixel potential Vdp as shown in FIG. 11 until the scanning voltage Vgh is applied in a next field (TF 2). On the other hand, since the counter electrode 101 is set at a predetermined counter potential VCOM by the counter electrode driving circuit COM, the liquid crystal material sealed between the pixel electrode 103 and the counter electrode 101 responds to a potential difference between the pixel potential Vdp and the counter potential VCOM, thus allowing image displaying to be performed.
Similarly, in the second field (TF 2), when the scanning voltage Vgh shown in FIG. 11 is applied from the scanning signal line driving circuit 300 to the scanning line G(j), the switching element 102 is turned on, a video signal voltage Vsn from the signal line driving circuit 200 is written into the pixel electrode 103, and a pixel potential Vdn is held. The liquid crystal material responds to a potential difference between the pixel potential Vdn and the counter potential VCOM, thus allowing image displaying to be performed. As a result, liquid crystal AC driving is achieved.
Now, since the foregoing constitution inevitably leads to the formation of the parasitic capacitance Cgd between the gate and the drain of the switching element 102 as shown in FIG. 10, level shifting (delta Vd) occurs in the pixel potential Vd because of the parasitic capacitance Cgd at the falling of the scanning voltage Vgh as shown in FIG. 11. If a non-scanning time voltage (off-time voltage of the switching element 102) of a scanning signal is Vgl, then the following equation is established for the level shifting (delta Vd) occurring in the pixel potential Vd because of the parasitic capacitance Cgd inevitably formed in the switching element 102:(delta Vd)=Cgd×(Vgh−Vgl)/(C1c+Cs+Cgd)Consequently, the level shifting causes problems including flicker and display deterioration on display images, which is not preferable for the liquid crystal display device directed to higher definition and quality.
Therefore, for example, it has been heretofore presented that the counter electrode 101 is biased to the counter potential VCOM by considering the level shifting (delta Vd) caused by the parasitic capacitance Cgd.
The scanning signal lines G(1), G(2), xxx G(j), xxx G(M) shown in FIGS. 8 and 9 are signal delay paths in which signal propagation delay occurs to a certain extent, because of the difficulty in formation thereof by ideal wires having no signal propagation delay.
FIG. 12 shows a propagation equivalent circuit when attention is paid to the signal propagation delay of one scanning signal line G(j). Reference numerals rg1, rg2, rg3, xxx rgN in FIG. 12 denote resistance components of a wire material forming the scanning signal line G(j), and resistance components based on wire widths and lengths. In addition, reference numerals cg1, cg2, cg3, xxx cgN denote various parasitic capacitances having capacitance coupling relations with the scanning signal line G(j) in terms of the constitution thereof. For example, the parasitic capacitances are composed of cross capacitances generated by crossing with the signal lines. Thus, the scanning signal line G(j) is a signal propagation delay path of a distribution constant type.
FIG. 13 shows a state where a scanning signal VG(j) inputted from the foregoing scanning signal line driving circuit 300 to the scanning signal line G(j) is deformed inside a panel because of the above-described signal propagation delay characteristic of the scanning signal line G(j). In FIG. 13, a waveform Vg(1, j) indicates a waveform of a scanning signal in a portion g(1, j) (see FIG. 12) in the vicinity of an input end on the scanning signal line G(j), exhibiting almost no waveform deformation. On the other hand, a waveform Vg(N, j) in the drawing indicates a waveform of a scanning signal in a portion g(N, j) (see FIG. 12) in the vicinity of a termination on the scanning signal line G(j). Compared with the waveform Vg(1, j), the waveform Vg(N, j) is more deformed because of the signal propagation delay characteristic of the scanning signal line G(j). This waveform deformation generates a changing amount SyN per unit time.
In addition, the switching element 102 composed of the TFT is not a complete on and off switch, and has a V-I characteristic (gate voltage-drain current characteristic) as shown in FIG. 14. In FIG. 14, an abscissa indicates a voltage Vg applied to the gate of the switching element 102; and an ordinate indicates a drain current Id. Normally, a scanning signal is composed of a rectangular pulse including a voltage level Vgh enough to turn on the switching element 102 and a voltage level Vgl enough to turn off the same. However, as shown in the drawing, an intermediate on area (linear area) is present from a threshold value VT of the switching element 102 to the Vgh level.
As shown in FIG. 13, the falling of the scanning signal from Vgh to Vgl instantaneously occurs in the pixel positioned in the vicinity of g(1,j)(see FIG. 12). Thus, there is no influence from the characteristic of the foregoing TFT linear area, and the level shifting (delta Vd(1)) occurring in the pixel potential Vd(1, j) because of the above-described parasitic capacitance Cgd can be approximated to the following:(delta Vd)=Cgd×(Vgh−Vgl)/(C1c+Cs+Cgd)
However, in the pixel positioned in the vicinity of g(N, j) (see FIG. 12) as the termination of the scanning signal line G(j), the scanning signal is deformed at the falling. Accordingly, there is influence from the characteristic of the TFT linear area, and no level shifting occurs in the pixel potential Vd caused by the parasitic capacitance Cgd. This is because the switching element 102 is on in the linear area while the scanning signal falls from Vgh to the vicinity of the threshold value level VT of the TFT. In an area where the scanning signal further changes from the vicinity of the threshold value level VT to Vgl, level shifting (delta Vd(N)) occurs in the pixel potential Vd(N, j) because of the above-described parasitic capacitance Cgd. Thus, the level shifting (delta Vd(N)) becomes as follows:(delta Vd(N))<Cgd×(Vgh−Vgl)/(C1c+Cs+Cgd)Then, the following is established:(delta Vd(1))>(delta Vd(N))
Therefore, the level shifting (delta Vd) occurring in the pixel potential Vd because of the parasitic capacitance Cgd in the panel becomes nonuniform in the display surface, which cannot be ignored along with achievement of a larger screen and higher definition. In other words, a counter voltage biasing method of the conventional system cannot absorb the nonuniformity of the level shifting in the display surface, and any pixels cannot be AC-driven optimally. Consequently, inconvenience inevitably occurs, such as the occurrence of flicker, a residual burned image by a DC component application and the like.
Thus, in the conventional case, methods described below have been presented in order to prevent the nonuniformity of the level shifting (delta Vd) in the display surface.
For example, a gazette of Japanese Patent Laid-Open Hei 11 (1999)-281957 discloses a technology for controlling a falling inclination of a scanning signal by adding a throughrate control element to an output stage of a gate driver. The throughrate control element enables a falling waveform of the output of the scanning signal to be optionally set based on a changing amount thereof per unit time.
A gazette of Japanese Patent Laid-Open Hei 6 (1994)-110035 discloses a technology for reducing nonuniformity of the level shifting (delta Vd) in the display surface by setting a falling waveform of a scanning signal to be a ramp waveform, an exponential waveform or a stair waveform so as to reduce high frequency components of the scanning signal, and thereby suppressing the level shifting (delta Vd) itself.
However, in such conventional technologies, a certain kind of circuit must be added inside the gate driver or between the gate driver and the scanning line, making it difficult to use general-purpose components, or complicating a circuitry. Consequently, manufacturing and cost problems are inevitable.